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1. general description the pcf8564a is a cmos 1 real-time clock and calendar optimized for low power consumption. a programmable clock output, interrupt output and voltage low detector are also provided. all addresses and data are transferred serially via the two-line bidirectional i 2 c-bus. maximum bus speed is 400 kbit/s. the built-in word address register is incremented automatically after each written or read data byte. 2. features and benefits ? provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 khz quartz crystal ? wide clock operating voltage: 1.0 v to 5.5 v ? low back-up current typical 250 na at 3.0 v and 25 ? c ? 400 khz two-wire i 2 c interface (1.8 v to 5.5 v) ? low-voltage detector ? alarm and timer functions ? two integrated os cillator capacitors ? programmable clock output for peripheral devices (32.768 khz, 1.024 khz, 32 hz, and 1hz) ? internal power-on reset (por) ? i 2 c slave address: read a3h, write a2h 3. applications ? timing devices ? time of the day tracking ? process timing ? alarm ? portable instruments ? electronic metering ? battery powered products pcf8564a real time clock and calendar rev. 3 ? 26 august 2013 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 20 .
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 2 of 48 nxp semiconductors pcf8564a real time clock and calendar 4. ordering information 4.1 ordering options [1] bump hardness, see table 36 . 5. marking table 1. ordering information type number package name description version pcf8564au bare die wire bond die; 9 bonding pads pcf8564au pcf8564aug bare die 9 bumps pcf8564aug table 2. ordering options product type number sales item (12nc) orderable part number ic revision delivery form pcf8564au/10ab/1 935289478005 pcf8564a u/10ab/1,0 1 wafer, sawn, on ffc pcf8564au/5bb/1 935289319015 pcf8564au/5bb/1,01 1 unsawn wafer pcf8564au/5gb/1 935289477015 pcf856 4au/5gb/1,01 1 unsawn wafer pcf8564au/5gc/1 935293569015 pcf856 4au/5gc/1,01 1 unsawn wafer pcf8564aug/12hb/1 935301011005 pcf8564aug/1 2hb/1v 1 wafer, sawn, on 8 inch metal ffc; chips with soft bumps [1] table 3. marking codes type number marking code pcf8564au pc8564a-1 pcf8564aug pc8564a-1
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 3 of 48 nxp semiconductors pcf8564a real time clock and calendar 6. block diagram fig 1. block diagram of pcf8564a ddk 3&)$ 26&,//$725 n+] ',9,'(5 &/2&.287 ,17(55837 &/.287 &/.2( ,17 021,725 32:(521 5(6(7 :$7&+ '2* , & ,17(5)$&( 26&, 6&/ 6'$ 26&2 9'' 966 7,0(5)81&7,21 7lphubfwuo (k 7lphu )k &21752/ &rqwurob k &rqwurob k &/.287bfwuo 'k 7,0( 6hfrqgv k 0lqxwhv k +rxuv k 'd\v k $/$50)81&7,21 0lqxwhbdodup k +rxubdodup $k 'd\bdodup %k :hhngd\bdodup &k :hhngd\v k 0rqwkv k <hduv k
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 4 of 48 nxp semiconductors pcf8564a real time clock and calendar 7. pinning information 7.1 pinning 7.2 pin description [1] the substrate (rear side of the die) is at v ss potential and must not be connected. viewed from active side. for mechanical details, see figure 27 and figure 28 . fig 2. pinning diagram of pcf8564a [ \ 3&)$ ddd 26&, 26&2 ,17 6'$ &/.287 9 '' &/.2( 6&/ 9 66 table 4. pin description input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin description osci 1 oscillator input osco 2 oscillator output int 3 interrupt output, open-drain, active low v ss 4 ground [1] sda 5 serial data input and output scl 6 serial clock input clkout 7 clock output, push-pull v dd 8 supply voltage clkoe 9 clkout enable input
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 5 of 48 nxp semiconductors pcf8564a real time clock and calendar 8. functional description the pcf8564a contains sixteen 8-bit r egisters with an auto-incrementing address register, an on-chip 32.768 khz oscillator wit h integrated capacitors, a frequency divider which provides the source clock for the rtc, a programmable clock output, a timer, a voltage low detector, and a 400 khz i 2 c-bus interface. all sixteen registers (see ta b l e 5 ) are designed as addressable 8-bit parallel registers although not all bits are implemented. the first two registers (memory address 00h and 01h) are used as control and/or status regist ers. the addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). address locations 09h through 0ch contain alarm registers which define the conditions for an alarm. address 0dh controls the clkout output frequency. 0eh and 0fh are the timer control and timer registers, respectively. the seconds, minutes, hours, days, months, ye ars, as well as the minute alarm, hour alarm, and day alarm registers are all coded in bcd format. 8.1 clkout output a programmable square wave is available at the clkout pin. frequencies of 32.768 khz, 1.024 khz, 32 hz and 1 hz c an be generated for use as a system clock, microcontroller clock, input to a charge pump, or fo r calibration of the oscillator. clkout is a cmos push-pull output, and if disabled it becomes logic 0.
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 6 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.2 register organization table 5. register overview bit positions labelled as - are not implemented. bit positions labelled as n should always be written with logic 0. after reset , all registers are set according to table 28 . address register name bit 7 6 5 4 3 2 1 0 control registers 00h control_1 test1 n stop n testc n n n 01h control_2 n n n ti_tp af tf aie tie time and date registers 02h seconds vl seconds (0 to 59) 03h minutes - minutes (0 to 59) 04h hours - - hours (0 to 23) 05h days - - days (1 to 31) 06h weekdays - - - - - weekdays 07h months c - - month (1 to 12) 08h years years (0 to 99) alarm registers 09h minute_alarm aen_m minute_alarm (0 to 59) 0ah hour_alarm aen_h - hour_alarm (0 to 23) 0bh day_alarm aen_d - day_alarm (1 to 31) 0ch weekday_alarm aen_w - - - - weekday_alarm clkout control register 0dhclkout_ctrlfe-----fd[1:0] timer registers 0eh timer_ctrl te - - - - - td[1:0] 0fh timer tv[7:0]
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 7 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.3 control registers 8.3.1 register control_1 [1] default value. [2] bits labeled as n should alwa ys be written with logic 0. 8.3.2 register control_2 [1] bits labeled as n should alwa ys be written with logic 0. [2] default value. table 6. control_1 - control and status re gister 1 (address 00h) bit description bit symbol value description reference 7 test1 0 [1] normal mode; ? must be set to logic 0 during normal operations section 8.9 1 ext_clk test mode (see section 8.9 ) 6n 0 [2] default value 5stop0 [1] rtc source clock runs section 8.10 1 ? rtc divider chain flip-flops are asynchronously set to logic 0 ? the rtc clock is stopped (clkout at 32.768 khz is still available) 4n 0 [2] default value 3 testc 0 power-on reset (por) override facility is disabled; ? set to logic 0 for normal operation (see section 8.11.1 ) section 8.11.1 1 [1] power-on reset (por) override is enabled 2 to 0 n 000 [2] default value table 7. control_2 - control and status re gister 2 (address 01h) bit description bit symbol value description reference 7to5 n 000 [1] default value 4ti_tp0 [2] int is active when tf is active (subject to the status of tie) 1int pulses active according to ta b l e 8 (subject to the status of tie); ? remark: note that if af and aie are active then int will be permanently active section 8.3.2.1 and section 8.8 3af 0 [2] alarm flag inactive section 8.3.2.1 1 alarm flag active 2tf 0 [2] timer flag inactive section 8.3.2.1 1 timer flag active 1aie 0 [2] alarm interrupt disabled section 8.3.2.1 1 alarm interrupt enabled 0tie 0 [2] timer interrupt disabled section 8.3.2.1 1 timer interrupt enabled
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 8 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.3.2.1 interrupt output bits tf and af: when an alarm occurs, af is set to 1. similarly, at the end of a timer countdown, tf is set to 1. these bits maintain their value until overwritten by command. if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one flag being overwritten while clearing another, a logic and is performed during a write access. bits tie and aie: these bits activate or deactivate the generation of an interrupt when tf or af is asserted respective ly. the interrupt is the logical or of these two conditions when both aie and tie are set. countdown timer interrupts: the pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value tv. as a consequence, the width of the interrupt pulse varies (see table 8 ). [1] tf and int become active simultaneously. [2] tv = loaded countdown value. timer is stopped when tv = 0. when bits tie and aie are disabled, pin int will remain high-impedance. fig 3. interrupt scheme ddd 7( &2817'2:1&2817(5 $)$/$50 )/$* &/($5 6(7 wrlqwhuidfh uhdg$) 7)7,0(5 &/($5 6(7 38/6( *(1(5$725 &/($5 75,**(5 7,( ,17 iurplqwhuidfh fohdu7) iurplqwhuidfh fohdu$) vhwdodup iodj$) wrlqwhuidfh uhdg7) 7,b73 $,( hj$,( table 8. int operation (bit ti_tp = 1) [1] source clock (hz) int period (s) tv = 1 [2] tv > 1 4096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 9 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.4 time and date registers the majority of the registers are coded in the bcd format to simplify application use. 8.4.1 register seconds [1] start-up value. 8.4.1.1 voltage low detector and clock monitor the pcf8564a has an on-chip voltage low detector. when v dd drops below v low the vl (voltage low) flag is set to indicate that the integrity of the clock information is no longer guaranteed. the vl flag can only be cleared by command. table 9. seconds - seconds and clock integrity status register (address 02h) bit description bit symbol value place value description 7 vl 0 - clock integrity is guaranteed 1 [1] - integrity of the clock information is not guaranteed 6 to 4 seconds 0 to 5 ten?s place actual seconds coded in bcd format, see ta b l e 1 0 3 to 0 0 to 9 unit place table 10. seconds coded in bcd format seconds value in decimal upper-digit (ten?s place) digit (unit place) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 0000000 01 0000001 02 0000010 : 09 0001001 10 0010000 : 58 1011000 59 1011001 fig 4. voltage low detection 9/vhw qrupdosrzhu rshudwlrq shulrgriedwwhu\ rshudwlrq w 9 '' 9 orz pju
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 10 of 48 nxp semiconductors pcf8564a real time clock and calendar the vl flag is intended to detect the situation when v dd is decreasing slowly, for example under battery o peration. should the os cillator stop or v dd reach v low before power is re-asserted, th en the vl flag will be set. this indicates that the ti me is possibly corrupted. 8.4.2 register minutes 8.4.3 register hours 8.4.4 register days [1] the pcf8564a compensates for leap years by adding a 29t h day to february if the year counter contains a value which is exactly divisi ble by 4, including the year 00. 8.4.5 register weekdays table 11. minutes - minutes regist er (address 03h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 ten?s place actual minutes coded in bcd format 3 to 0 0 to 9 unit place table 12. hours - hours register (address 04h) bit description bit symbol value place value description 7 to 6 - - - unused 5 to 4 hours 0 to 2 ten?s place actual hours coded in bcd format 3 to 0 0 to 9 unit place table 13. days - days register (address 05h) bit description bit symbol value place value description 7 to 6 - - - unused 5to4 days [1] 0 to 3 ten?s place actual day coded in bcd format 3 to 0 0 to 9 unit place table 14. weekdays - weekdays register (address 06h) bit description bit symbol value description 7 to 3 - - unused 2 to 0 weekdays 0 to 6 actual weekday values, see ta b l e 1 5
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 11 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] definition may be re-assigned by the user. 8.4.6 register months [1] this bit may be re-assigned by the user. [2] this bit is toggled when the regist er years overflows from 99 to 00. table 15. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday110 table 16. months - months and century flag register (address 07h) bit description bit symbol value place value description 7c [1] 0 [2] - indicates the century is x 1 - indicates the century is x + 1 6 to 5 - - - unused 4 months 0 to 1 ten?s place actual month coded in bcd format, see table 17 3 to 0 0 to 9 unit place table 17. month assignments coded in bcd format month upper-digit (ten?s place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april00100 may00101 june00110 july00111 august01000 september 0 1 0 0 1 october10000 november10001 december10010
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 12 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.4.7 register years [1] when the register years overflows from 99 to 00, t he century bit c in the register months is toggled. the pcf8564a compensates for leap years by adding a 29th day to february if the year counter contains a value which is divisible by 4, including the year 00. 8.5 setting and reading the time figure 5 shows the data flow and data dependenci es starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. this prevents ? faulty writing or reading of the clock and calendar during a carry condition ? incrementing the time registers, during the read cycle after this read/write access is completed, the time circuit is released again and any pending request to increment the time counters, that occurred during the read access, is serviced. a maximum of 1 request can be st ored; therefore, all accesses must be completed within 1 second (see figure 6 ). table 18. years - years register (08h) bit description bit symbol value place value description 7 to 4 years 0 to 9 ten?s place actual year coded in bcd format [1] 3to0 0to9 unit place fig 5. data flow for the time function ddd +]wlfn :((.'$< 6(&21'6 0,187(6 +2856 '$<6 /($3<($5 &$/&8/$7,21 0217+6 <($56 &
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 13 of 48 nxp semiconductors pcf8564a real time clock and calendar as a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method co uld result in the time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. a similar problem exists when reading. a roll over may occur between reads thus giving the minutes from one moment and the hours from the next. recommended method for reading the time: 1. send a start condition and the slave address for write (a2h). 2. set the address pointer to 2 (seconds) by sending 02h. 3. send a re-start condition or stop followed by start. 4. send the slave address for read (a3h). 5. read the seconds. 6. read the minutes. 7. read the hours. 8. read the days. 9. read the weekdays. 10. read the century and month. 11. read the years. 12. send a stop condition. 8.6 alarm registers 8.6.1 register minute_alarm [1] default value. fig 6. access time for read/write operations wv ddd 6/$9($''5(66 '$7$ 6723 '$7$ 67$57 table 19. minute_alarm - minute alarm register (address 09h) bit description bit symbol value place value description 7 aen_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 ten?s place minute alarm information coded in bcd format 3 to 0 0 to 9 unit place
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 14 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.6.2 register hour_alarm [1] default value. 8.6.3 register day_alarm [1] default value. 8.6.4 register weekday_alarm [1] default value. 8.6.5 alarm flag by clearing the msb of one or more of t he alarm registers aen_x (alarm enable), the corresponding alarm condition(s) are active. when an alarm occurs, af is set to logic 1. the asserted af can be used to generate an interrupt (int ). the af is cleared by command. the registers at addresses 09h through 0ch contain alarm information. when one or more of these registers is loaded with a valid minute, hour, day, or weekday and its corresponding alarm enable bit (aen_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday. when all enabled comparisons first match, the alarm flag (af in register control_2) is set to logic 1. table 20. hour_alarm - hour alarm regist er (address 0ah) bit description bit symbol value place value description 7 aen_h 0 - hour alarm is enabled 1 [1] - hour alarm is disabled 6 - - - unused 5 to 4 hour_alarm 0 to 2 ten?s place hour alarm information coded in bcd format 3 to 0 0 to 9 unit place table 21. day_alarm - day alarm register (address 0bh) bit description bit symbol value place value description 7 aen_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 ten?s place day alarm information coded in bcd format 3 to 0 0 to 9 unit place table 22. weekday_alarm - weekday alarm re gister (address 0ch) bit description bit symbol value description 7 aen_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information coded in bcd format
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 15 of 48 nxp semiconductors pcf8564a real time clock and calendar the generation of interrupts from the alarm func tion is controlled via bit aie. if bit aie is enabled, the int pin follows the condition of bit af . af will remain set until cleared by command. once af has been clear ed, it will only be set agai n when the time increments to match the alarm condition once more. al arm registers which have their aen_x bit at logic 1 are ignored. 8.7 register clkout_ctrl and clock output a programmable square wave is available at pin clkout. operation is controlled by the fe bit in register clkout_ctrl at address 0dh and the clkout output enable pin (clkoe). to enable pin clkout pin clkoe must be set high. frequencies of 32.768 khz ( default), 1.024 khz, 32 hz, and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. (1) only when all enabled alarm settings are matching. it?s only on increment to a matched case that the alarm flag is set, see section 8.6.5 . fig 7. alarm function block diagram ddd :((. '$<$/$50 $(1b: :((.'$<7,0( '$<$/$50 $(1b' '$<7,0( +285$/$50 $(1b+ +2857,0( 0,187($/$50 $(1b0 0,187(7,0( fkhfnqrzvljqdo vhwdodupiodj$) $(1b0 h[dpsoh
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 16 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] default value. 8.8 timer function the 8-bit countdown timer at address 0fh is controlled by the timer control register at address 0eh. the timer control register deter mines one of 4 source clock frequencies for the timer (4.096 khz, 64 hz, 1 hz, or 1 60 hz) and enables or disables the timer. the timer counts down from a software-loaded 8-bit binary value. at the end of every countdown, the timer sets the tf (timer flag) to logic 1. the tf may only be cleared using the interface. the generation of interrupts from the timer func tion is controlled via bit tie. if bit tie is enabled the int pin follows the condition of bit tf. the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of the timer flag tf. ti_tp is used for this mode c ontrol. when reading the timer, the current countdown value is returned. 8.8.1 register timer_ctrl [1] default value. [2] these bits determine the source clock for the countdow n timer; when not in use, td[1:0] should be set to 1 60 hz for power saving. table 23. clkout_ctrl - clkout control register (address 0dh) bit description bit symbol value description 7 fe 0 the clkout output is inhi bited and clkout output is set to logic 0 1 [1] the clkout output is activated 6 to 2 - - unused 1 to 0 fd[1:0] frequency output at pin clkout 00 [1] 32.768 khz 01 1.024 khz 10 32 hz 11 1 hz table 24. timer_ctrl - timer control register (address 0eh) bit description bit symbol value description 7te 0 [1] timer is disabled 1 timer is enabled 6 to 2 - - unused 1 to 0 td[1:0] timer source clock frequency select [2] 00 4.096 khz 01 64 hz 10 1 hz 11 [2] 1 60 hz
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 17 of 48 nxp semiconductors pcf8564a real time clock and calendar 8.8.2 register timer [1] countdown period in seconds: where tv is the countdown timer value. the timer register is an 8-bit binary countdown timer. it is enabled or disabled via the timer control register. the source clock for the timer is also selected by the timer control register. other timer properties such as si ngle or periodic interrupt generation are controlled via the register control_2 (address 01h). for accurate read back of the count down value, the i 2 c-bus clock (sda) must be operating at a frequency of at least twice the se lected timer clock. since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. 8.9 ext_clk test mode the test mode is entered by setting the test1 bit of register control_1 to logic 1. the clkout pin then becomes an input. the test mode replaces the internal 64 hz signal with that applied to the clkout pin. every 64 positive edges applied to clkout then generates an increment of one second. the signal applied to the clkout pin should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the 64 hz cl ock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler. the prescaler can be set to a known state by using the stop bit. when the stop bit is set, the prescale r is reset to logic 0. (stop must be cleared before the prescaler can operate.) from a stop condition, the first 1 second increment will take place after 32 positive edges on clkout. thereafter, every 64 posi tive edges will cause a 1 second increment. remark: entry into ext_clk test mode is not syn chronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. 8.9.1 operation example 1. set ext_clk test mode (bit 7 control_1 = 1). 2. set stop (bit 5 control_1 = 1). 3. clear stop (bit 5 control_1 = 0). 4. set time registers to desired value. 5. apply 32 clock pulses to clkout. table 25. timer - timer register (address 0fh) bit description bit symbol value description 7to0 tv[7:0] 0htoffh countdown timer value [1] table 26. timer register bits value range bit 7 6 5 4 3 2 1 0 1286432168421 countdownperiod tv sourceclockfrequency -------------------------------------------------------------- - =
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 18 of 48 nxp semiconductors pcf8564a real time clock and calendar 6. read time registers to see the first change. 7. apply 64 clock pulses to clkout. 8. read time registers to see the second change. repeat 7 and 8 for additional increments. 8.10 stop bit function the function of the stop bit is to allow for accurate starting of the time circuits. the stop bit function will caus e the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks will be genera ted (see figure 8 ). the time circuits can then be set and will not increment until the stop bit is released (see figure 9 and table 27 ). the stop bit function will not af fect the output of 32.768 khz on clkout, but will stop the generation of 1.024 khz, 32 hz and 1 hz. the lower two stages of the prescaler (f 0 and f 1 ) are not reset and because the i 2 c-bus is asynchronous to the crystal oscillator, the ac curacy of re-starting the time circuits will be between zero and one 8.192 khz cycle (see figure 9 ). fig 8. stop bit functional diagram ddd 26&,//$725 +] +] 26&,//$7256723 '(7(&725 ) ) ) 5(6(7 ) 5(6(7 ) 5(6(7 +] +] +] +]wlfn 6723 &/.287vrxufh uhvhw +] +] +] +] fig 9. stop bit release timing ddi +] vwrsuhohdvhg ?vwr?v
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 19 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] f 0 is clocked at 32.768 khz. the first increment of the time circuits is between 0.507813 s and 0.507935 s after stop bit is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see table 27 ) and the unknown state of the 32 khz clock. 8.11 reset the pcf8564a includes an internal reset circuit which is active whenever the oscillator is stopped. in the reset state the i 2 c-bus logic is initialized including the address pointer and all registers are set according to ta b l e 2 8 . i 2 c-bus communication is not possible during reset. table 27. first increment of time circuits after stop bit release bit prescaler bits [1] 1hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 - xx-0 1000 0000 0000 08:00:00 - xx-1 1000 0000 0000 08:00:00 - : :: 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f 14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : :: 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : :- 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f 14 increments the time circuits ddd wrv v
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 20 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] registers marked ?x? are undefined at power-on and unchanged by subsequent resets. 8.11.1 power-on reset (por) override the por duration is directly rela ted to the crystal o scillator start-up time. due to the long start-up times experienced by these types of circuits, a circuit has been implemented to disable the por and speed up functional test of the module. the setting of this mode requires that the i 2 c signals on the pins sda and scl are toggled as illustrated in figure 10 . all timings shown are required minimums. once the override mode has been entered, the chip immediately stops, being reset, and normal operation may begin, i.e., entry into the ext_clk test mode via i 2 c access. the override mode may be cleared by writing logic 0 to testc. testc must be set to logic 1 before re-entry into the override mode is po ssible. setting testc to logic 0 during normal operation has no effect, except to prev ent entry into the por override mode. table 28. register reset values [1] address register name bit 7 6 5 4 3 2 1 0 00h control_1 00001000 01h control_2 00000000 02h seconds 1xxxxxxx 03h minutes xxxxxxxx 04h hours xxxxxxxx 05h days xxxxxxxx 06h weekdays xxxxxxxx 07h months xxxxxxxx 08h years xxxxxxxx 09h minute_alarm 1xxxxxxx 0ahhour_alarm 1xxxxxxx 0bhday_alarm 1xxxxxxx 0chweekday_alarm1xxxxxxx 0dhclkout_ctrl 1xxxxx00 0ehtimer_ctrl 0xxxxx11 0fhtimer xxxxxxxx allow 500 ns between the edges of either signal. fig 10. por override sequence pjp 6&/ qv qv 6'$ pv ryhuulghdfwlyh srzhurq
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 21 of 48 nxp semiconductors pcf8564a real time clock and calendar 9. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 11 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as the start condition (s). a low-to-high transition of the data line, while the clock is high, is defined as the stop condition (p), see figure 12 . 9.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves (see figure 13 ). fig 11. bit transfer pef gdwdolqh vwdeoh gdwdydolg fkdqjh rigdwd doorzhg 6'$ 6&/ fig 12. definition of start and stop conditions pef 6'$ 6&/ 3 6723frqglwlrq 6'$ 6&/ 6 67$57frqglwlrq
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 22 of 48 nxp semiconductors pcf8564a real time clock and calendar 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 14 . fig 13. system configuration ped 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 0$67(5 75$160,77(5 5(&(,9(5 6'$ 6&/ fig 14. acknowledgment on the i 2 c-bus pef 6 67$57 frqglwlrq forfnsxovhiru dfnqrzohgjhphqw qrwdfnqrzohgjh dfnqrzohgjh gdwdrxwsxw e\wudqvplwwhu gdwdrxwsxw e\uhfhlyhu 6&/iurp pdvwhu
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 23 of 48 nxp semiconductors pcf8564a real time clock and calendar 10. i 2 c-bus protocol 10.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always ca rried out with the first byte transmitted after the start procedure. the pcf8564a acts as a slave receiver or sl ave transmitter. therefore, the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. two slave addresses are reserved for the pcf8564a: read: a3h (1010 0011) write: a2h (1010 0010) the pcf8564a slave address is shown in figure 14 . 10.2 clock and calendar read or write cycles figure 16 , figure 17 , and figure 18 show the i 2 c-bus configuration for the different pcf8564a read and write cycles. the word address is a 4-bit value that defines which register is to be accessed next. the upper four bits of the word address are not used. fig 15. slave address pfh 5: jurxs jurxs fig 16. master transmits to slave receiver (write mode) 6 $ 6/$9($''5(66 :25'$''5(66 $ $ '$7$ 3 dfnqrzohgjhphqw iurpvodyh dfnqrzohgjhphqw iurpvodyh dfnqrzohgjhphqw iurpvodyh 5: dxwrlqfuhphqw phpru\zrugdgguhvv peg qe\whv
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 24 of 48 nxp semiconductors pcf8564a real time clock and calendar fig 17. master reads word after setting word address (write word address; read data) 6 $ 6/$9($''5(66 :25'$''5(66 $ $ 6/$9($''5(66 dfnqrzohgjhphqw iurpvodyh 5: $ ddd 3 5: 6 dfnqrzohgjhphqw iurpvodyh dfnqrzohgjhphqw iurpvodyh dfnqrzohgjhphqw iurppdvwhu qrdfnqrzohgjhphqw iurppdvwhu dxwrlqfuhphqw phpru\zrugdgguhvv dxwrlqfuhphqw phpru\zrugdgguhvv dwwklvprphqwpdvwhuwudqvplwwhu ehfrphvpdvwhuuhfhlyhudqg 3&)$vodyhuhfhlyhu ehfrphvvodyhwudqvplwwhu odvwe\wh '$7$ '$7$ qe\whv fig 18. master reads slave immediatel y after first byte (read mode) 6 $ 6/$9($''5(66 '$7$ $ '$7$ dfnqrzohgjhphqw iurpvodyh dfnqrzohgjhphqw iurppdvwhu qrdfnqrzohgjhphqw iurppdvwhu 5: dxwrlqfuhphqw zrugdgguhvv pjo dxwrlqfuhphqw zrugdgguhvv qe\whv odvwe\wh 3
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 25 of 48 nxp semiconductors pcf8564a real time clock and calendar 10.3 interface watchdog timer during read/write operations, the time counting circuits are frozen. to prevent a situation where the accessing device becomes locked and does not clear the interface, the pcf8564a has a built in watchdog timer. should the interface be active for more than 1 s from the time a valid slave ad dress is transmitted, then the pcf8564a will automatically clear the interface and allow the time counting circuits to continue counting. the watchdog will trigger between 1 s and 2 s after receivin g a valid slave address. each time the watchdog period is exceeded, 1 s will be lost from the time counters. the watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is remove d from a battery backed-up system during an interface access. a. correct data transfer: read or write b. incorrect data transfer; read or write fig 19. interface watchdog timer ddd 6/$9($''5(66 uxqqlqj wlph frxqwhuv :'wlphu gdwd :'wlphuwudfnlqj wlphfrxqwhuviur]hq uxqqlqj '$7$ wv '$7$ 6723 67$57 ddd 6/$9($''5(66 uxqqlqj wlph frxqwhuv :'wlphu gdwd :'wlphuwudfnlqj wlphfrxqwhuviur]hq uxqqlqj '$7$ vwv '$7$ 67$57 gdwdwudqvihuidlo :'wulsv
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 26 of 48 nxp semiconductors pcf8564a real time clock and calendar 11. internal circuitry 12. safety notes fig 20. device diode protection diagram ddd 6'$ 6&/ 9 '' &/.2( 26&, 26&2 9 66 3&)$ ,17 &/.287 caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. caution semiconductors are light sens itive. exposure to light s ources can cause the ic to malfunction. the ic must be protected agains t light. the protection must be applied to all sides of the ic.
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 27 of 48 nxp semiconductors pcf8564a real time clock and calendar 13. limiting values [1] pass level; human body model (hbm) according to ref. 5 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 6 ? jesd22-a115 ? . [3] pass level; latch-up testing, according to ref. 7 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport conditions (see ref. 11 ? um10569 ? ) the devices have to be stored at a temperature of +5 ? c to +45 ? c and a humidity of 25 % to 75 %. table 29. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v i input voltage ? 0.5 +6.5 v v o output voltage ? 0.5 +6.5 v i dd supply current ? 50.0 +50.0 ma i i input current ? 10.0 +10.0 ma i o output current ? 10.0 +10.0 ma i ss ground supply current ? 50.0 +50.0 ma p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm [1] - ? 3500 v mm [2] - ? 250 v i lu latch-up current all pins but osci [3] -1 0 0m a t stg storage temperature [4] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +85 ?c
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 28 of 48 nxp semiconductors pcf8564a real time clock and calendar 14. static characteristics table 30. static characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage interface inactive; t amb =25 ?c [1] 1.0- 5.5v interface active; f scl = 400 khz [1] 1.8- 5.5v for clock data integrity; t amb =25 ?c v low -5 . 5v i dd supply current interface active f scl =400khz - - 800 ? a f scl =100khz - - 200 ? a interface inactive (f scl =0hz); clkout disabled; t amb =25 ?c [2] [3] [4] v dd = 5.0 v - 275 550 na v dd = 3.0 v - 250 500 na v dd = 2.0 v - 225 450 na interface inactive (f scl =0hz); clkout disabled; t amb = ? 40 ? cto +85 ?c [2] [3] [4] v dd = 5.0 v - 500 750 na v dd = 3.0 v - 400 650 na v dd = 2.0 v - 400 600 na interface inactive (f scl =0hz); clkout enabled at 32 khz; t amb =25 ?c [4] [5] [6] v dd = 5.0 v - 1500 3000 na v dd = 3.0 v - 1000 2000 na v dd = 2.0 v - 700 1400 na interface inactive (f scl =0hz); clkout enabled at 32 khz; t amb = ? 40 ? cto +85 ?c [4] [5] [6] v dd = 5.0 v - 1700 3400 na v dd = 3.0 v - 1100 2200 na v dd = 2.0 v - 800 1600 na inputs v i input voltage on pins sda and scl ? 0.5 - +5.5 v on pins clkoe and clkout (test mode) ? 0.5 - v dd +0.5 v v il low-level input voltage - - 0.3v dd v v ih high-level input voltage 0.7v dd --v
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 29 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] for reliable oscillator start-up at power-on: v dd(po)min =v dd(min) +0.3v. [2] timer source clock = 1 60 hz. [3] clkout disabled (fe = 0 or clkoe = 0). [4] v il and v ih with an input voltage swing of v ss to v dd . [5] clkout is open circuit. [6] current consumption when the clkout pin is enabled is a f unction of the load on the pin, the output frequency, and the suppl y voltage. the additional current consumption for a given load is calculated from: . [7] tested on sample basis. i li input leakage current v i = v ss or v dd -0- ? a post esd event ? 1- +1 ? a c i input capacitance [7] --7p f outputs v o output voltage on pin clkout ? 0.5 - v dd +0.5 v on pin int ? 0.5 - +5.5 v i ol low-level output current on pin sda; v ol =0.4v; v dd =5v 3- - ma on pin int ; v ol =0.4v; v dd =5v ? 1- - ma on pin clkout: v ol =0.4v; v dd =5v ? 1- - ma i oh high-level output current on pin clkout; v oh =4.6v; v dd =5v 1- - ma i lo output leakage current v o =v ss or v dd -0- ? a post esd event ? 1- +1 ? a voltage detector v low low voltage t amb =25 ?c- 0 . 9 1 . 0 v table 30. static characteristics ?continued v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit i dd cv dd f clkout ?? =
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 30 of 48 nxp semiconductors pcf8564a real time clock and calendar t amb =25 ? c; timer = 1 minute; clkout disabled. t amb =25 ? c; timer = 1 minute; clkout = 32 khz. fig 21. i dd as a function of v dd fig 22. i dd as a function of v dd v dd = 3 v; timer = 1 minute; clkout = 32 khz. t amb =25 ? c; normalized to v dd =3v. fig 23. i dd as a function of temperature fig 24. frequency deviation as a function of v dd pju 9 '' 9 , '' ?$ pju 9 '' 9 , '' ?$ pju 7?& , '' ?$ pju 9 '' 9 iuhtxhqf\ ghyldwlrq ssp
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 31 of 48 nxp semiconductors pcf8564a real time clock and calendar 15. dynamic characteristics [1] integrated load capacitance, c l(itg) , is a calculation of c osci and c osco in series: . [2] unspecified for f clkout = 32.768 khz. [3] all timing values are valid within the operating supply voltage at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . [4] a detailed description of the i 2 c-bus specification is given in ref. 9 ? um10204 ? . table 31. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit oscillator c l(itg) integrated load capacitance [1] 6810pf ? f osc /f osc relative oscilla tor frequency variation ? v dd =200mv; t amb =25 ?c -0 . 2-p p m quartz crystal parameters r s series resistance - - 100 k ? c l load capacitance - 8 - pf clkout output ? clkout duty cycle on pin clkout [2] -5 0-% i 2 c-bus timing char acteristics (see figure 25 ) [3] [4] f scl scl clock frequency - - 400 khz t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t r rise time of both sda and scl signals --0.3 ? s t f fall time of both sda and scl signals --0.3 ? s c b capacitive load for each bus line - - 400 pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t w(spike) spike pulse width - - 50 ns c litg ?? c osci c osco ? ?? c osci c osco + ?? ------------------------------------------- - =
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 32 of 48 nxp semiconductors pcf8564a real time clock and calendar 16. application information fig 25. i 2 c-bus timing waveforms 6'$ pjd 6'$ 6&/ w 6867$ w 68672 w +'67$ w %8) w /2: w +''$7 w +,*+ w u w i w 68'$7 connect clkoe to an appropriate level. a 1 farad super capacitor combined with a low v f diode can be used as a standby or back-up supply. with the rtc in its minimum power configuration, the rtc may operate for weeks. fig 26. application diagram ddd 6&/ 6'$ 9 66 26&, 26&2 &/2&.&$/(1'$5 3&)$ 6'$ 6&/ 0$67(5 75$160,77(5 5(&(,9(5 9 '' 9 '' 6'$ 6&/ 55 9 '' , &exv )
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 33 of 48 nxp semiconductors pcf8564a real time clock and calendar 17. bare die outline fig 27. bare die outline of pcf8564au/x 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 3&)$8 sfidxbgr 1rwh 0dunlqjfrgh3&$ )ljxuhqrwgudzqwrvfdoh :luherqgglherqglqjsdgv 3&)$8 $ ghwdlo; 3 3 3 3 h h h ; \ [ ' (
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 34 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] depending on wafer thickness, see table 37 . table 32. dimensions of pcf8564au/x chip dimensions including saw line. original dimensions are in mm. unit (mm) a d e e e 1 e 2 p 1 p 2 p 3 p 4 max ---------- nom [1] 1.26 1.89 1.05 0.22 0. 9 0.1 0.09 0.1 0.09 min ----------
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 35 of 48 nxp semiconductors pcf8564a real time clock and calendar fig 28. bare die outline of pcf8564aug/x 5hihuhqfhv 2xwolqh yhuvlrq (xurshdq surmhfwlrq ,vvxhgdwh ,(& -('(& -(,7$ 3&)$8* sfidxjbgr 1rwh 0dunlqjfrgh3&$ )ljxuhqrwgudzqwrvfdoh %duhglhexpsv 3&)$8* ghwdlo; 3 3 h h h ; \ [ ' ( ghwdlo< $ $ $ <
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 36 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] depending on wafer thickness, see table 37 . table 33. dimensions of pcf8564aug/x chip dimensions including saw line. original dimensions are in mm. unit (mm) a a 1 a 2 d e e e 1 e 2 p 1 p 2 max ---------- nom [1] 0.015 [1] 1.26 1.89 1.05 0.22 0.9 0.09 0.09 min ----------
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 37 of 48 nxp semiconductors pcf8564a real time clock and calendar [1] pressure of diamond head: 10 g to 50 g. table 34. pin location of all pcf8564a types all x/y coordinates represent the pos ition of the center of each pin wit h respect to the center (x/y = 0) of the chip; see figure 27 and figure 28 . symbol pad x ( ? m) y ( ? m) description osci 1 ? 523.0 689.4 oscillator input osco 2 ? 523.0 469.4 oscillator output int 3 ? 523.0 ? 429.8 open-drain interrupt output (active low) v ss 4 ? 523.0 ? 684.4 ground (substrate) sda 5 524.9 ? 523.8 serial data i/o scl 6 524.9 ? 138.6 serial clock input clkout 7 524.9 162.5 cmos push-pull clock output v dd 8 524.9 443.3 supply clkoe 9 524.9 716.3 clkout output enable fig 29. alignment marks of all pcf8564a types table 35. alignment marks of all pcf8564a types all x/y coordinates represent the position of the ref point (see figure 29 ) with respect to the center (x/y = 0) of the chip; see figure 27 and figure 28 . alignment markers size ( ? m) x (? m) y ( ? m) c1 100 ? 100 465.2 ? 826.3 c2 100 ? 100 ? 523.0 890.0 f90 ? 117 ? 569.9 ? 885.5 table 36. gold bump hardness type number min max unit [1] pcf8564aug/12hb/1 35 80 hv 5() 5() & & ) ddd 5()
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 38 of 48 nxp semiconductors pcf8564a real time clock and calendar 18. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards.
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 39 of 48 nxp semiconductors pcf8564a real time clock and calendar 19. packing information 19.1 wafer and film frame carrier (ffc) information wafer thickness, see table 37 . fig 30. wafer layout of pcf8564a ; 6dzodqh ghwdlo; 0dunlqjfrgh 6wudljkwhgjh riwkhzdihu ddd 3lq ?p ?p 6hdoulqjsoxvjdswr dfwlyhflufxlwa?p ?p ?p
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 40 of 48 nxp semiconductors pcf8564a real time clock and calendar table 37. pcf8564a wafer information type number wafer thickness wafer diameter ffc for wafer size marking of bad die pcf8564au/5bb/1 0.28 mm 6 inch - inking pcf8564au/5gb/1 0.69 mm 6 inch - inking pcf8564au/5gc/1 0.69 mm 6 inch - wafer mapping pcf8564au/10ab/1 0.20 mm 6 inch 6 inch inking pcf8564aug/12hb/1 0.15 mm 6 inch 8 inch inking fig 31. film frame carrier (ffc) for 6 inch wafer (pcf8564au/10ab/1) ddd pp pp pp ?pp ?pp pp pp phwdoiudph sodvwlfilop vwudljkwhgjh riwkhzdihu
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 41 of 48 nxp semiconductors pcf8564a real time clock and calendar fig 32. film frame carrier (ffc) for 8 inch wafer (pcf8564aug/12hb/1) ddd ppsodvwln ppphwdoo pp pp ?pp ? pp pp pp iudph sodvwlfilop vwudljkwhgjh riwkhzdihu
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 42 of 48 nxp semiconductors pcf8564a real time clock and calendar 20. abbreviations 21. references [1] an10439 ? wafer level chip size package [2] an10706 ? handling bare die [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [7] jesd78 ? ic latch-up test [8] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [9] um10204 ? i 2 c-bus specification and user manual [10] um10301 ? user manual for nxp real time clocks pcf85x3, pca8565 and pcf2123, pca2125 [11] um10569 ? store and transport requirements table 38. abbreviations acronym description bcd binary coded decimal cmos complementary metal oxide semiconductor ffc film frame carrier hbm human body model i 2 c inter-integrated circuit ic integrated circuit lsb least significant bit mm machine model mos metal oxide semiconductor msb most significant bit msl moisture sensitivity level pcb printed-circuit board por power-on reset rom read only memory rtc real time clock scl serial clock line sda serial data line
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 43 of 48 nxp semiconductors pcf8564a real time clock and calendar 22. revision history table 39. revision history document id release date data sheet status change notice supersedes pcf8564a v.3 20130826 product data sheet - pcf8564a v.2 modifications: ? adjusted product and ordering information ? added figure 19 pcf8564a v.2 20100930 product data sheet - pcf8564a v.1 pcf8564a v.1 20091008 product data sheet - -
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 44 of 48 nxp semiconductors pcf8564a real time clock and calendar 23. legal information 23.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 23.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 23.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 45 of 48 nxp semiconductors pcf8564a real time clock and calendar export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 23.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 24. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 46 of 48 nxp semiconductors pcf8564a real time clock and calendar 25. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 5. register overview . . . . . . . . . . . . . . . . . . . . . . . .6 table 6. control_1 - contro l and status register 1 (address 00h) bit description . . . . . . . . . . . . . . .7 table 7. control_2 - contro l and status register 2 (address 01h) bit description . . . . . . . . . . . . . . .7 table 8. int operation (bit ti_tp = 1) [1] . . . . . . . . . . . . . .8 table 9. seconds - seconds and clock integrity status register (address 02h) bit description . . . . . . . . .9 table 10. seconds coded in bcd format . . . . . . . . . . . . .9 table 11. minutes - minutes register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 12. hours - hours register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 13. days - days register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 14. weekdays - weekdays register (address 06h) bit description . . . . . . . . . . . . . .10 table 15. weekday assignments . . . . . . . . . . . . . . . . . . 11 table 16. months - months and century flag register (address 07h) bit description . . . . . . . . . . . . . . 11 table 17. month assignments coded in bcd format . . . 11 table 18. years - years register (08h) bit description . . . .12 table 19. minute_alarm - minute alarm register (address 09h) bit description . . . . . . . . . . . . . .13 table 20. hour_alarm - hour alarm register (address 0ah) bit description . . . . . . . . . . . . . .14 table 21. day_alarm - day alarm register (address 0bh) bit description . . . . . . . . . . . . . .14 table 22. weekday_alarm - weekday alarm register (address 0ch) bit description . . . . . . . . . . . . . .14 table 23. clkout_ctrl - clkout control register (address 0dh) bit description . . . . . . . . . . . . . .16 table 24. timer_ctrl - timer control register (address 0eh) bit description . . . . . . . . . . . . . .16 table 25. timer - timer register (address 0fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .17 table 26. timer register bits value range . . . . . . . . . . . . .17 table 27. first increment of time circuits after stop bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 28. register reset values [1] . . . . . . . . . . . . . . . . . .20 table 29. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27 table 30. static characteristics . . . . . . . . . . . . . . . . . . . .28 table 31. dynamic characteristics . . . . . . . . . . . . . . . . . .31 table 32. dimensions of pcf8564au/x . . . . . . . . . . . . .34 table 33. dimensions of pcf8564aug/x . . . . . . . . . . .36 table 34. pin location of all pcf8564a types . . . . . . . .37 table 35. alignment marks of all pcf8564a types . . . . .37 table 36. gold bump hardness . . . . . . . . . . . . . . . . . . . .37 table 37. pcf8564a wafer informati on . . . . . . . . . . . . . .40 table 38. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 39. revision history . . . . . . . . . . . . . . . . . . . . . . . .43
pcf8564a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 26 august 2013 47 of 48 nxp semiconductors pcf8564a real time clock and calendar 26. figures fig 1. block diagram of pcf8564a . . . . . . . . . . . . . . . . .3 fig 2. pinning diagram of pcf8564a . . . . . . . . . . . . . . .4 fig 3. interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8 fig 4. voltage low detection . . . . . . . . . . . . . . . . . . . . . . .9 fig 5. data flow for the time function . . . . . . . . . . . . . . .12 fig 6. access time for read/write operations . . . . . . . . .13 fig 7. alarm function block diagram. . . . . . . . . . . . . . . .15 fig 8. stop bit functional diagram . . . . . . . . . . . . . . . .18 fig 9. stop bit release timing . . . . . . . . . . . . . . . . . . . .18 fig 10. por override sequence . . . . . . . . . . . . . . . . . . .20 fig 11. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 fig 12. definition of start and stop conditions. . . . . .21 fig 13. system configuration . . . . . . . . . . . . . . . . . . . . . .22 fig 14. acknowledgment on the i 2 c-bus . . . . . . . . . . . . .22 fig 15. slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23 fig 16. master transmits to slave receiver (write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .23 fig 17. master reads word after setting word address (write word address; read dat a) . . . . . . . . . . . .24 fig 18. master reads slave immediately after first byte (read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 19. interface watchdog timer . . . . . . . . . . . . . . . . . . .25 fig 20. device diode protection di agram . . . . . . . . . . . . .26 fig 21. i dd as a function of v dd . . . . . . . . . . . . . . . . . . . .30 fig 22. i dd as a function of v dd . . . . . . . . . . . . . . . . . . . .30 fig 23. i dd as a function of temperature . . . . . . . . . . . . .30 fig 24. frequency deviation as a function of v dd . . . . . .30 fig 25. i 2 c-bus timing waveforms . . . . . . . . . . . . . . . . . .32 fig 26. application diagram . . . . . . . . . . . . . . . . . . . . . . .32 fig 27. bare die outline of pcf8 564au/x . . . . . . . . . . . .33 fig 28. bare die outline of pcf8 564aug/x . . . . . . . . . . .35 fig 29. alignment marks of all pcf8564a types . . . . . . .37 fig 30. wafer layout of pcf8564a . . . . . . . . . . . . . . . . .39 fig 31. film frame carrier (ffc) for 6 inch wafer (pcf8564au/10ab/1) . . . . . . . . . . . . . . . . . . . . .40 fig 32. film frame carrier (ffc) for 8 inch wafer (pcf8564aug/12hb/1) . . . . . . . . . . . . . . . . . . .41
nxp semiconductors pcf8564a real time clock and calendar ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 26 august 2013 document identifier: pcf8564a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 27. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 clkout output . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 register organization . . . . . . . . . . . . . . . . . . . . 6 8.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 register control_1 . . . . . . . . . . . . . . . . . . . . . . 7 8.3.2 register control_2 . . . . . . . . . . . . . . . . . . . . . . 7 8.3.2.1 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.4 time and date registers . . . . . . . . . . . . . . . . . . 9 8.4.1 register seconds . . . . . . . . . . . . . . . . . . . . . . . 9 8.4.1.1 voltage low detector and clock monitor . . . . . . 9 8.4.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 10 8.4.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 10 8.4.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.4.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 10 8.4.6 register months . . . . . . . . . . . . . . . . . . . . . . . 11 8.4.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 setting and reading the time. . . . . . . . . . . . . . 12 8.6 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6.1 register minute_alarm . . . . . . . . . . . . . . . . . . 13 8.6.2 register hour_alarm . . . . . . . . . . . . . . . . . . . 14 8.6.3 register day_alarm . . . . . . . . . . . . . . . . . . . . 14 8.6.4 register weekday_alarm . . . . . . . . . . . . . . . . 14 8.6.5 alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.7 register clkout_ctrl and clock output. . . . . 15 8.8 timer function . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.8.1 register timer_ctrl . . . . . . . . . . . . . . . . . . . . . 16 8.8.2 register timer . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 ext_clk test mode . . . . . . . . . . . . . . . . . . . . 17 8.9.1 operation example . . . . . . . . . . . . . . . . . . . . . 17 8.10 stop bit function . . . . . . . . . . . . . . . . . . . . . . 18 8.11 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11.1 power-on reset (por) override . . . . . . . . . . 20 9 characteristics of the i 2 c-bus . . . . . . . . . . . . 21 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 start and stop conditions . . . . . . . . . . . . . 21 9.3 system configuration . . . . . . . . . . . . . . . . . . . 21 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.2 clock and calendar read or write cycles . 23 10.3 interface watchdog timer . . . . . . . . . . . . . . . . 25 11 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26 12 safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27 14 static characteristics . . . . . . . . . . . . . . . . . . . 28 15 dynamic characteristics. . . . . . . . . . . . . . . . . 31 16 application information . . . . . . . . . . . . . . . . . 32 17 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 33 18 handling information . . . . . . . . . . . . . . . . . . . 38 19 packing information . . . . . . . . . . . . . . . . . . . . 39 19.1 wafer and film frame carrier (ffc) information. . . . . . . . . . . . . . . . . . . . . . 39 20 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42 21 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 23 legal information . . . . . . . . . . . . . . . . . . . . . . 44 23.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 23.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 24 contact information . . . . . . . . . . . . . . . . . . . . 45 25 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 27 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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